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this is information on a product in full production. december 2014 docid13863 rev 3 1/15 l6385e high voltage high and low-side driver datasheet - production data features ? high voltage rail up to 600 v ? dv/dt immunity 50 v/nsec in full temperature range ? driver current capability: ? 400 ma source ? 650 ma sink ? switching times 50/30 nsec rise/fall with 1 nf load ? cmos/ttl schmitt trigger inputs with hysteresis and pull-down ? undervoltage lockout on lower and upper driving section ? internal bootstrap diode ? outputs in phase with inputs applications ? home appliances ? induction heating ? hvac ? motor drivers ? sr motors ? dc, ac, pmdc and pmac motors ? asymmetrical half-bridge topologies ? industrial applications and drives ? lighting applications ? factory automation ? power supply systems description the l6385e is a simple and compact high voltage gate driver, manufactured with the bcd? ?offline? technology, and able to drive a half-bridge of power mosfet or igbt devices. the high-side (floating) section is able to work with voltage rail up to 600 v. both device outputs can independently sink and source 650 ma and 400 ma respectively and can be simultaneously driven high. the l6385e device provides two input pins and two output pins and guarantees the outputs toggle in phase with inputs. the logic inputs are cmos/ttl compatible to ease the interfacing with controlling devices. the bootstrap diode is integrated inside the device, allowing a more compact and reliable solution. the l6385e features the uvlo protection on both lower and upper driving sections (v cc and v boot ), ensuring greater protection against voltage drops on the supply lines. the device is available in a dip-8 tube and so-8 tube, and tape and reel packaging options. dip-8 so-8 table 1. device summary part number package packaging l6385e dip-8 tube l6385ed so-8 tube L6385ED013TR so-8 tape and reel www.st.com
contents l6385e 2/15 docid13863 rev 3 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1 ac operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 dc operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.3 timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 c boot selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 typical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
docid13863 rev 3 3/15 l6385e block diagram 15 1 block diagram figure 1. block diagram logic uv detection level shifter bootstrap driver r r s v cc lvg driver v cc 8 7 6 5 4 hin lin hvg driver hvg h.v. to load out lvg gnd d97in514b vboot 3 2 1 cboot uv detection
electrical data l6385e 4/15 docid13863 rev 3 2 electrical data 2.1 absolute maximum ratings 2.2 thermal data 2.3 recommended operating conditions table 2. absolute maximum ratings symbol parameter value unit v out output voltage -3 to v boot -18 v v cc supply voltage - 0.3 to +18 v v boot floating supply voltage -1 to 618 v v hvg high-side gate output voltage -1 to v boot v v lvg low-side gate output voltage -0.3 to v cc +0.3 v v i logic input voltage -0.3 to v cc +0.3 v dv out /d t allowed output slew rate 50 v/ns p tot total power dissipation (t j = 85 c) 750 mw t j junction temperature 150 c t s storage temperature -50 to 150 c table 3. thermal data symbol parameter so-8 dip-8 unit r th(ja) thermal resistance junction to ambient 150 100 c/w table 4. recommended operating conditions symbol pin parameter test condition min. typ. max. unit v out 6 output voltage (1) 1. if the condition v boot - v out < 18 v is guaranteed, v out can range from -3 to 580 v. 580 v v bs (2) 2. v bs = v boot - v out . 8 floating supply voltage (1) 17 v f sw switching frequency hvg,lvg load c l = 1 nf 400 khz v cc 3 supply voltage 17 v t j junction temperature -45 125 c
docid13863 rev 3 5/15 l6385e pin connection 15 3 pin connection figure 2. pin connection (top view) table 5. pin description no. pin type function 1 lin i low-side driver logic input 2 hin i high-side driver logic input 3 v cc p low voltage power supply 4 gnd p ground 5 lvg (1) 1. the circuit guarantees 0.3 v maximum on the pin (at isink = 10 ma). this allows to omit the ?bleeder? resistor connected between the gate and the source of the external mosfet normally used to hold the pin low. o low-side driver output 6 out p high-side driver floating reference 7 hvg (1) o high-side driver output 8 v boot p bootstrap supply voltage v cc hin lin gnd 1 3 2 4 lvg out hvg v boot 8 7 6 5 d97in517a
electrical characteristics l6385e 6/15 docid13863 rev 3 4 electrical characteristics 4.1 ac operation 4.2 dc operation table 6. ac operation electrical characteristics (v cc = 15 v; t j = 25 c) symbol pin parameter test condition min. typ. max. unit t on 1 vs. 5 2 vs. 7 high/low-side driver turn-on propagation delay v out = 0 v 110 ns t off 1 vs. 5 2 vs. 7 high/low-side driver turn-off propagation delay v out = 0 v 105 ns t r 5, 7 rise time c l = 1000 pf 50 ns t f 5, 7 fall time c l = 1000 pf 30 ns table 7. dc operation electrical characteristics (v cc = 15 v; t j = 25 c) symbol pin parameter test condition min. typ. max. unit low supply voltage section v cc 3 supply voltage 17 v v ccth1 v cc uv turn-on threshold 9.1 9.6 10.1 v v ccth2 v cc uv turn-off threshold 7.9 8.3 8.8 v v cchys v cc uv hysteresis 1.3 v i qccu undervoltage quiescent supply current v cc ? 9 v 150 220 ? a i qcc quiescent current v in = 15 v 250 320 ? a r dson bootstrap driver on resistance (1) v cc ? 12.5 v 125 ? bootstrapped supply voltage section v bs 8 bootstrap supply voltage 17 v v bsth1 v bs uv turn-on threshold 8.5 9.5 10.5 v v bsth2 v bs uv turn-off threshold 7.2 8.2 9.2 v v bshys v bs uv hysteresis 1.3 v i qbs v bs quiescent current hvg on 200 ? a i lk high voltage leakage current v hvg = v out = v boot = 600 v 10 ? a high/low-side driver i so 5, 7 source short-circuit current v in = v ih (t p < 10 ? s) 300 400 ma i si sink short-circuit current v in = v il (tp < 10 ? s) 450 650 ma
docid13863 rev 3 7/15 l6385e electrical characteristics 15 4.3 timing diagram figure 3. input/output timing diagram symbol pin parameter test condition min. typ. max. unit logic inputs v il 1, 2 low level logic threshold voltage 1.5 v v ih high level logic threshold voltage 3.6 v i ih 1, 2 high level logic input current v in = 15 v 50 70 ? a i il low level logic input current v in = 0 v 1 ? a 1. r ds(on) is tested in the following way: where i 1 is pin 8 current when v cboot = v cboot1 , i 2 when v cboot = v cboot2 . table 7. dc operation electrical characteristics (v cc = 15 v; t j = 25 c) (continued) r dson v cc v cboot1 ? ?? v cc v cboot2 ? ?? ? i 1 v cc ,v cboot1 ?? i 2 v cc ,v cboot2 ?? ? ------------------------------------------------------------------------------------------------------ - = hin hvg lvg lin d99in1053
bootstrap driver l6385e 8/15 docid13863 rev 3 5 bootstrap driver a bootstrap circuitry is needed to supply the high voltage section. this function is normally accomplished by a high voltage fast recovery diode ( figure 4 a). in the l6385e device a patented integrated structure replaces the exte rnal diode. it is realized by a high voltage dmos, driven synchronously with the low-side driver (lvg), with a diode in series, as shown in figure 4 b. an internal charge pump ( figure 4 b) provides the dmos driving voltage. the diode connected in series to the dmos has been added to avoid undesirable turn-on. c boot selection and charging to choose the proper c boot value, the external mos can be seen as an equivalent capacitor. this capacitor c ext is related to the mos total gate charge: equation 1 the ratio between the capacitors c ext and c boot is proportional to the cyclical voltage loss. it has to be: c boot >>>c ext e.g.: if q gate is 30nc and v gate is 10v, c ext is 3nf. with c boot = 100nf the drop would be 300 mv. if hvg has to be supplied for a long time, the c boot selection has to take into account also the leakage losses. e.g.: hvg steady state consumption is lower than 200 ? a, so if hvg t on is 5 ms, c boot has to supply a maximum of 1 c to c ext . this charge on a 1mf capacitor means a voltage drop of 1 v. the internal bootstrap driver gives great adv antages: the external fast recovery diode can be avoided (it usually has a great leakage current). this structure can work only if v out is close to gnd (or lower) and in the meanwhile the lvg is on. the charging time (t charge ) of the c boot is the time in whic h both conditions are fulfilled and it has to be long enough to charge the capacitor. the bootstrap driver introduces a voltage drop due to the dmos r dson (typical value: 125 ? ). at low frequency this drop can be negl ected. anyway increasing the frequency it must be taken in to account. the following equation is useful to compute the drop on the bootstrap dmos: equation 2 where q gate is the gate charge of the external power mos, r dson is the on resistance of the bootstrap dmos, and t charge is the charging time of the bootstrap capacitor. c ext q gate v gate -------------- - = v drop i ch e arg r dson v drop ? q gate t ch e arg ------------------- r dson ==
docid13863 rev 3 9/15 l6385e bootstrap driver 15 for example: using a power mos with a total gate charge of 30 nc the drop on the bootstrap dmos is about 1 v, if the t charge is 5 ms. in fact: equation 3 v drop has to be taken into account when the voltage drop on c boot is calculated: if this drop is too high, or the circuit topology doesn?t allo w a sufficient charging time, an external diode can be used. figure 4. bootstrap driver v drop 30nc 5 ? s -------------- - 125 ? 0.8v ? ? = to load d99in1056 h.v. hvg ab lvg hvg lvg c boot to load h.v. c boot d boot v boot v s v s v out v boot v out
typical characteristic l6385e 10/15 docid13863 rev 3 6 typical characteristic figure 5. typical rise and fall times vs. load capacitance figure 6. quiescent current vs. supply voltage figure 7. turn-on time vs. temperature figure 8. turn-off time vs. temperature figure 9. v boot uv turn-on threshold vs. temperature figure 10. v cc uv turn-off threshold vs. temperature for both high and low side buffers @25?c tamb 0 1 2 3 4 5 c (nf) 0 50 100 150 200 250 time (nsec) tr d99in1054 tf 0 2 4 6 8 10 12 14 16 v s (v) 10 10 2 10 3 10 4 iq ( a) d99in1055 -45 -25 0 25 50 75 100 125 0 50 100 150 200 250 ton (ns) tj (c) typ. @ vcc = 15v -45 -25 0 25 50 75 100 125 0 50 100 150 200 250 toff (ns) tj (c) typ. @ vcc = 15v -45 -25 0 25 50 75 100 125 5 6 7 8 9 10 11 12 13 vbth1 (v) tj (c) typ. @ vcc = 15v -45 -25 0 25 50 75 100 125 6 7 8 9 10 11 vccth2(v) tj (c) typ.
docid13863 rev 3 11/15 l6385e typical characteristic 15 figure 11. v boot uv turn-off threshold vs. temperature figure 12. output source current vs. temperature figure 13. v cc uv turn-on threshold vs. temperature figure 14. output sink current vs. temperature -45 -25 0 25 50 75 100 125 6 7 8 9 10 11 12 13 14 vbth2 (v) typ. @ vcc = 15v -45 -25 0 25 50 75 100 125 0 200 400 600 800 1000 current (ma) tj (c) typ. @ vcc = 15v -45 -25 0 25 50 75 100 125 0 200 400 600 800 1000 current (ma) tj (c) typ. @ vcc = 15v -45 -25 0 25 50 75 100 125 7 8 9 10 11 12 13 vccth1(v) tj (c) typ. -45 -25 0 25 50 75 100 125 0 200 400 600 800 1000 current (ma) tj (c) typ. @ vcc = 15v
package information l6385e 12/15 docid13863 rev 3 7 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions a nd product status are available at: www.st.com . ecopack is an st trademark. figure 15. dip-8 package outline table 8. dip-8 package mechanical data symbol dimensions (mm) dimensions (inch) min. typ. max. min. typ. max. a 3.32 0.131 a1 0.51 0.020 b 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 d 10.92 0.430 e 7.95 9.75 0.313 0.384 e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 f 6.6 0.260 i 5.08 0.200 l 3.18 3.81 0.125 0.150 z 1.52 0.060
docid13863 rev 3 13/15 l6385e package information 15 figure 16. so-8 package outline table 9. so-8 package mechanical data symbol dimensions (mm) dimensions (inch) min. typ. max. min. typ. max. a 1.750 0.0689 a1 0.100 0.250 0.0039 0.0098 a2 1.250 0.0492 b 0.280 0.480 0.0110 0.0189 c 0.170 0.230 0.0067 0.0091 d (1) 1. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 mm in total (both sides). 4.800 4.900 5.000 0.1890 0.1929 0.1969 e 5.800 6.000 6.200 0.2283 0.2362 0.2441 e1 (2) 2. dimension ?e1? does not include in terlead flash or protrusions. interl ead flash or protrusions shall not exceed 0.25 mm per side. 3.800 3.900 4.000 0.1496 0.1535 0.1575 e 1.270 0.0500 h 0.250 0.500 0.0098 0.0197 l 0.400 1.270 0.0157 0.0500 l1 1.040 0.0409 k0808 ccc 0.10 0.0039 $09
revision history l6385e 14/15 docid13863 rev 3 8 revision history table 10. document revision history date revision changes 02-oct-2007 1 first release 19-jun-2014 2 added section : applications on page 1 . updated section : description on page 1 (replaced by new description). updated table 1: device summary on page 1 (moved from page 15 to page 1, renamed title of table 1 ). updated figure 1: block diagram on page 3 (moved from page 1 to page 3, added section 1: block diagram on page 3 ). updated section 2.1: absolute ma ximum ratings on page 4 (removed note below table 2: absolute maximum ratings ). updated table 5: pin description on page 5 (updated ?pin? and ?type?). updated section : c boot selection and charging on page 8 (updated values of ?e.g.: hvg?). numbered equation 1 on page 8 , equation 2 on page 8 and equation 3 on page 9 . updated section 7: package information on page 12 [updated/added titles, reversed order of figure 15 and table 8 , figure 16 and table 9 (numbered tables), removed 3d package figures, minor modifications]. minor modifications throughout document. 01-dec-2014 3 updated section : description on page 1 . updated table 7 on page 6 (corrected typo in units of ? i so ? and ?i si ? parameters).
docid13863 rev 3 15/15 l6385e 15 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

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